Author:Zujind Kazir
Language:English (Spanish)
Published (Last):22 April 2006
PDF File Size:6.48 Mb
ePub File Size:10.13 Mb
Price:Free* [*Free Regsitration Required]

For input voltages less than 7 V, the regulator saturates within 1 V of the input and tracks it see Figure 4.

The comparator has a response time of ns from either of the control-signal inputs to the output dien tu cong suat, with only mV of overdrive. The TL combines many features that previously required several different control circuits. A Internal offset Figure 8. Both high-gain error amplifiers receive their bias from the V I supply rail.

In addition to providing a stable reference, it acts as a preregulator and establishes a stable supply dien tu cong suat which the output-control logic, pulse-steering flip-flop, oscillator, dead-time control comparator, and PWM comparator are powered. The PWM comparator compares the control signal created by the error amplifiers. Figure 1 is a block diagram dien tu cong suat the TL With full-range control, the output can be controlled from external sources without disrupting the error amplifiers.

The timing capacitor input incorporates a series diode that is omitted from the control signal input. For push-pull applications, the output frequency is one-half the oscillator frequency. The error amplifiers dienn can be used dien tu cong suat monitor the output current and provide current limiting to the load. This provides isolation from the input supply for improved stability.

Figure 2 shows the relationship between the pulses and the signals. TL Modulation Technique The control signals are derived from two sources: An in-depth study dien tu cong suat the interrelationship between the functional blocks highlights versatility and limitations of the TL The two functions are totally independent, therefore, each function is discussed separately.

Otherwise, the maximum output pulse width is limited. The dead-time ccong input is compared directly by the dead-time control comparator. This permits a common-mode input voltage range from —0. This comparator has a fixed mV offset.

Reference Voltage vs Input Voltage 3. A general overview of the TL architecture presents the primary functional blocks contained in the device. The purpose of this application report is to give the reader a thorough understanding of the TL, its features, its performance characteristics, and its limitations.

With the control input biased to ground, the output is inhibited during the dien tu cong suat that the sawtooth waveform is below mV. This cojg each amplifier to pull up independently for a decreasing output pulse-width demand. The amplifier outputs are biased low by a current sink to provide maximum pulse width out when both amplifiers are biased off. The charging current is fu by the formula: The oscillator charges the external timing capacitor, C Twith a constant current, dien tu cong suat value of which is determined by the external timing resistor, R T.

Multiplex Structure of Error Dien tu cong suat Figure A pulse-steering flip-flop alternately directs the modulated pulse to each of the two output transistors. Figure 7 shows diwn relationship of internal dead time expressed in percent for various values of R T and C T. Dien tu cong suat output of the comparator inhibits switching transistors Q1 and Q2 when the voltage at t input is greater than the ramp voltage of the oscillator see Figure For this, the ramp voltage across timing capacitor C T is compared to the control signal present at the output of the error amplifiers.

Related Articles


giáo trình điện tử công suất



Điện tử công suất, Dụng cụ, phụ kiện điện



Cách tính công suất của máy phát điện 1 pha, 3 pha


Related Articles