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Technology for Java? NOTE: This is a summary document. The complete document is available on the Atmel website at www. Required Power Supplies — 1. Two external buses prevent bottlenecks, thus guaranteeing maximum performance.
Signal Description Table gives details on the signal name classified by peripheral. Table Figure NC pins must be left unconnected. Power Considerations 5. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. This allows the device to reach its maximum speed, either out of 1.
The other signals control, address and data signals do not go over 50MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3. However, the device cannot reach its maximum speed if the voltage supplied to the pins is only 1. It integrates a permanent pull-down resistor of about 15 k?
Driving this line at a high level leads to unpredictable results. It has no action on the processor. The pin WKUP is an input only. Processor and Architecture 7. DSP Instruction Extensions? Programmable Arbitration strategy — Fixed-priority Arbitration — Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master? One Address Decoder provided per Master — Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap?
Each master has its own decoder, which is defined specifically for each master. Each slave has its own arbiter, thus allowing to program a different arbitration per slave.
They share the same layer, as programming them does not require a high bandwidth. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals.
Acts as one Matrix Master? Allows data transfers between a peripheral and memory without any intervention of the processor? Next Pointer support, removes heavy real-time constraints on buffer management. Embeds 2 unidirectional channels with programmable priority? Writing a stream of data into non-contiguous fields in system memory.
Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface? Memories Figure Decoding breaks up the 4G bytes of address space into 16 banks of M bytes. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M bytes of internal memory area.
Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each master has its own bus and its own decoder, thus allowing a different memory mapping for each master. However, in order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 ARM Instruction and Data , three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. A complete memory map is presented in Figure on page This internal SRAM is split into three areas.
Its memory mapping is presented in Figure on page Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes as shown in Table Table illustrates different configurations and the related 16 Kbyte blocks assignments RB0 to RB4. Configuration after reset. Boot Strategies The system always boot at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. This is done by software once the system has booted.
This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure on page Boot at slow clock?
Auto baudrate detection? Downloads and runs an application from external storage media into internal SRAM? Downloaded code size depends on embedded SRAM size? Automatic detection of valid application? The customer-programmed software must perform a complete configuration. Program the PMC main oscillator enable or bypass mode.
Program and Start the PLL. Switch the main clock to the new value. Each Chip Select line has a Mbyte memory area assigned. Refer to Figure on page External Bus Interface 0? Optimized for Application Memory Space support? Optional Full bit External Data Bus? Up to bit Address Bus up to 64 Mbytes linear per chip select? Up to bit Address Bus up to 8 Mbytes linear? Slow Clock mode supported 8. Energy-saving capabilities — Self-refresh, power down and deep power down modes supported?
Error detection — Refresh Error Interrupt? CAS Latency of 1, 2 and 3 supported? Auto Precharge Command not used 8. Single-bit error correction and two-bit random detection? Automatic Hamming Code Calculation while reading — Error Report, including error flag, correctable error flag and word address being detected erroneous — Support 8- or bit NAND Flash devices with , , or byte pages 9.
System Controller The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of registers for the chip configuration. However, all the registers of the System Controller are mapped on the top of the address space. Figure on page 27 shows the System Controller block diagram. Figure on page 20 shows the mapping of the User Interfaces of the System Controller peripherals.
Controls the internal resets and the NRST pin output — Allows shaping a reset signal for the external devices 9. Five flexible operating modes: — Normal Mode with processor and peripherals running at a programmable frequency — Idle Mode with processor stopped while waiting for an interrupt — Slow Clock Mode with processor and peripherals running at low frequency — Standby Mode, mix of Idle and Backup Mode, with peripherals running at low frequency, processor stopped waiting for an interrupt — Backup Mode with Main Power Supplies off, VDDBU powered by a battery Figure Includes a bit Periodic Counter, with less than 1?
Includes a bit Interval Overlay Counter? Real-time OS or Linux? Windowed, prevents the processor deadlocking on the watchdog access 9. Two Real-time Timers, allowing backup of time with different accuracies — bit Free-running back-up counter — Integrates a bit programmable prescaler running on the embedded Twenty bit general-purpose backup registers 9.
Four External Sources plus the Fast Interrupt signal? Protect Mode — Easy debugging by preventing automatic operations when protect models are enabled? Fast Forcing — Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.
Chip ID: 0xA0? Peripherals Each User Peripheral is allocated 16 Kbytes of address space. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. However, there is no clock control associated with these peripheral IDs. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently.